The SY89251V is a differential PECL/ECL receiver/buffer in a space saving (2mm x 2mm) DFN package. The device is functionally equivalent to the SY100EL16VC, except for an active HIGH enable pin and a 70% smaller footprint. It is also equivalent to the SY89250V, except for an active HIGH enable pin. It provides a VBB output for either single-ended application or as a DC bias for AC-coupling to the device.The SY89251V provides an EN input which is synchronized with the data input (D) signal in a way that provides glitchless gating of the QHG and /QHG outputs. When the EN signal is HIGH, the input is passed to the outputs and the data output equals the data input. When the data input is HIGH and the EN goes LOW, it will force the QHG LOW and the /QHG HIGH on the next negative transition of the data input. If the data input is LOW when the EN goes LOW, the next data transition to a HIGH is ignored and QHG remains LOW and /QHG remains HIGH. The next positive transition of the data input is not passed on to the data outputs under these conditions. The QHG and /QHG outputs remain in their disabled state as long as the EN input is held LOW. The EN input has no influence on the /Q output and the data input is passed on (inverted) to this output whether EN is HIGH or LOW. This configuration is ideal for crystal oscillator applications, where the oscillator can be free running and gated on and off synchronously without adding extra counts to the output.