SY100EP111 Series

2.5V/3.3V 1:10 Differential LVPECL/LVECL/HSTL Clock Fanout Buffer

Catalog

2.5V/3.3V 1:10 Differential LVPECL/LVECL/HSTL Clock Fanout Buffer

Part	Output	Input Ratio	Output Ratio	Mounting Type	Frequency - Max	Voltage - Supply (Maximum)	Voltage - Supply (Minimum)	Operating Temperature (Min)	Operating Temperature (Max)	Differential Input	Differential Output	Number of Circuits	Package / Case	Package Width	Package Name	Package Length	Input	Type
Microchip Technology SY100EP111UTI	LVECL LVPECL	2	10	Surface Mount	3 GHz	3.8 V	2.375 V	-40 °C	85 °C	Yes	Yes	1	32-TQFP	7 mm	32-TQFP	7 mm	HSTL LVECL LVPECL	Fanout Buffer (Distribution) Multiplexer
Microchip Technology SY100EP111UTG-TR	LVECL LVPECL	2	10	Surface Mount	3 GHz	3.8 V	2.375 V	-40 °C	85 °C	Yes	Yes	1	32-TQFP	7 mm	32-TQFP	7 mm	HSTL LVECL LVPECL	Fanout Buffer (Distribution) Multiplexer
Microchip Technology SY100EP111UTG	LVECL LVPECL	2	10	Surface Mount	3 GHz	3.8 V	2.375 V	-40 °C	85 °C	Yes	Yes	1	32-TQFP	7 mm	32-TQFP	7 mm	HSTL LVECL LVPECL	Fanout Buffer (Distribution) Multiplexer
Microchip Technology SY100EP111UTI-TR	LVECL LVPECL	2	10	Surface Mount	3 GHz	3.8 V	2.375 V	-40 °C	85 °C	Yes	Yes	1	32-TQFP	7 mm	32-TQFP	7 mm	HSTL LVECL LVPECL	Fanout Buffer (Distribution) Multiplexer
Microchip Technology SY100EP111UTG-TX	LVECL LVPECL	2	10	Surface Mount	3 GHz	3.8 V	2.375 V	-40 °C	85 °C	Yes	Yes	1	32-TQFP	7 mm	32-TQFP	7 mm	HSTL LVECL LVPECL	Fanout Buffer (Distribution) Multiplexer

Catalog

2.5V/3.3V 1:10 Differential LVPECL/LVECL/HSTL Clock Fanout Buffer

Description

The SY100EP111U is a high-speed, low skew 1-to-10 differential fanout buffer designed for clock distribution in new, high-performance systems. The internal 2:1 MUX allows the input to select between two differential clock sources. The device is specifically designed for low skew. The interconnect scheme and metal layout are carefully optimized for minimal gate-to-gate skew within the device. Wafer characterization and process control ensure consistent distribution of propagation delay from lot to lot.