SN74ABT16827 Series
20-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs
Manufacturer: Texas Instruments
Catalog
20-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs
Key Features
• Members of the Texas InstrumentsWidebusTMFamilyState-of-the-ArtEPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationLatch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Typical VOLP(Output Ground Bounce) < 1 V at VCC= 5 V, TA= 25°CHigh-Impedance State During Power Up and Power DownDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoiseFlow-Through Architecture Optimizes PCB LayoutHigh-Drive Outputs (-32-mA IOH, 64-mA IOL)Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center SpacingsWidebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.Members of the Texas InstrumentsWidebusTMFamilyState-of-the-ArtEPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationLatch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Typical VOLP(Output Ground Bounce) < 1 V at VCC= 5 V, TA= 25°CHigh-Impedance State During Power Up and Power DownDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoiseFlow-Through Architecture Optimizes PCB LayoutHigh-Drive Outputs (-32-mA IOH, 64-mA IOL)Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center SpacingsWidebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.
Description
AI
The 'ABT16827 are noninverting 20-bit buffers composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\ or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.
When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16827 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16827 is characterized for operation from -40°C to 85°C.
The 'ABT16827 are noninverting 20-bit buffers composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\ or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.
When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16827 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16827 is characterized for operation from -40°C to 85°C.