Technical Specifications
Parameters and characteristics for this part
| Specification | SPC560D30L1B4E0X | 
|---|---|
| Connectivity | SPI, CANbus, LINbus, UART/USART | 
| Core Processor | e200z0h | 
| Core Size | 32-Bit Single-Core | 
| Data Converters [custom] | 16 | 
| Data Converters [custom] | 12 b | 
| Grade | Automotive | 
| Mounting Type | Surface Mount | 
| Number of I/O | 45 | 
| Operating Temperature [Max] | 105 °C | 
| Operating Temperature [Min] | -40 °C | 
| Oscillator Type | Internal | 
| Package / Case | 64-LQFP | 
| Peripherals | DMA, LVD, PWM, POR, WDT | 
| Program Memory Size | 128 KB | 
| Program Memory Type | FLASH | 
| Qualification | AEC-Q100 | 
| RAM Size | 12 K | 
| Speed | 48 MHz | 
| Supplier Device Package | 64-LQFP (10x10) | 
| Voltage - Supply (Vcc/Vdd) [Max] | 5.5 V | 
| Voltage - Supply (Vcc/Vdd) [Min] | 3 V | 
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Description
General part information
SPC560D30L1B4E0X
These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices designed to be central to the development of the next wave of central vehicle body controller, smart junction box, front module, peripheral body, door control and seat control applications.This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture technology and designed specifically for embedded applications.The advanced and cost-efficient e200z0h host processor core of this automotive controller family complies with the Power Architecture technology and only implements the VLE (variable-length encoding) APU (auxiliary processing unit), providing improved code density. It operates at speeds of up to 48 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with the user’s implementations.The device platform has a single level of memory hierarchy and can support a wide range of on-chip static random access memory (SRAM) and internal flash memory.High-performance up to 48 MHz e200z0h CPU32-bit Power Architecture® technology CPUVariable length encoding (VLE)MemoryUp to 256 KB Code Flash with ECCUp to 64 (4x16) KB Data Flash with ECCUp to 16 KB SRAM with ECCInterrupts16 priority levelsNon-maskable interrupt (NMI)Up to 38 external interrupts incl. 18 wakeup lines16-channel eDMAGPIOs: 45 (LQFP64), 79 (LQFP100)Timer units4-channel 32-bit periodic interrupt timers4-channel 32-bit system timer moduleSystem watchdog timer32 bit real-time clock timer16-bit counter time-triggered I/OsUp to 28 channels with PWM/MC/IC/OC5 independent counters27 ch. with ADC trigger capability12-bit analog-to-digital converter (ADC) with up to 33 channelsUp to 61 channels via external multiplexingIndividual conversion registers
Documents
Technical documentation and resources
