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LTC2221CUP#TRPBF - 64-QFN

LTC2221CUP#TRPBF

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Analog Devices

IC ADC 12BIT PIPELINED 64QFN

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LTC2221CUP#TRPBF - 64-QFN

LTC2221CUP#TRPBF

Active
Analog Devices

IC ADC 12BIT PIPELINED 64QFN

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Technical Specifications

Parameters and characteristics for this part

SpecificationLTC2221CUP#TRPBF
ArchitecturePipelined
ConfigurationS/H-ADC
Data InterfaceLVDS - Parallel, Parallel
Input TypeSingle Ended, Differential
Mounting TypeSurface Mount
Number of A/D Converters1
Number of Bits12 bits
Number of Inputs1
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Package / Case64-WFQFN Exposed Pad
Ratio - S/H:ADC1:1
Reference TypeExternal, Internal
Sampling Rate (Per Second)135 M
Supplier Device Package64-QFN (9x9)
Voltage - Supply, Analog [Max]3.5 V
Voltage - Supply, Analog [Min]3.1 V
Voltage - Supply, Digital [Max]3.5 V
Voltage - Supply, Digital [Min]3.1 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTape & Reel (TR) 2000$ 60.06

Description

General part information

LTC2221 Series

The LTC2220 and LTC2221 are 170Msps/135Msps, sampling 12-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2220/LTC2221 are perfect for demanding communications applications with AC performance that includes 67.5dB SNR and 80dB spurious free dynamic range for signals up to 170MHz. Ultralow jitter of 0.15psRMSallows undersampling of IF frequencies with excellent noise performance.DC specs include ±0.4LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.5LSBRMS.The digital outputs can be either differential LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V.The ENC+and ENC–inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.ApplicationsWireless and Wired Broadband CommunicationCable Head-End SystemsPower Amplifier LinearizationCommunications Test Equipment