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LTC2215IUP#PBF - 64-QFN

LTC2215IUP#PBF

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Analog Devices

16-BIT, 65MSPS LOW NOISE ADC

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LTC2215IUP#PBF - 64-QFN

LTC2215IUP#PBF

Active
Analog Devices

16-BIT, 65MSPS LOW NOISE ADC

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationLTC2215IUP#PBF
ArchitecturePipelined
ConfigurationS/H-ADC
Data InterfaceLVDS - Parallel, Parallel
FeaturesPGA
Input TypeDifferential
Mounting TypeSurface Mount
Number of A/D Converters1
Number of Bits16
Number of Inputs1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case64-WFQFN Exposed Pad
Ratio - S/H:ADC1:1
Reference TypeExternal, Internal
Sampling Rate (Per Second)65 M
Supplier Device Package64-QFN (9x9)
Voltage - Supply, Analog [Max]3.465 V
Voltage - Supply, Analog [Min]3.135 V
Voltage - Supply, Digital [Max]3.465 V
Voltage - Supply, Digital [Min]3.135 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 129.04
10$ 105.32
25$ 100.31

Description

General part information

LTC2215 Series

The LTC2216/LTC2215 are 80Msps/65Msps sampling 16- bit A/D converters designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 400MHz. The input range of the ADC is fixed at 2.75VP-P.The LTC2216/LTC2215 are perfect for demanding communications applications, with AC performance that includes 81.5dBFS noise floor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 85fsRMSallows undersampling of high input frequencies while maintaining excellent noise performance. Maximum DC specs include ±3.5LSB INL, ±1LSB DNL (no missing codes).The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V.The ENC+and ENC–inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles.ApplicationsTelecommunicationsReceiversCellular Base StationsSpectrum AnalysisImaging SystemsATE

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