1894KI-40LF
Active10BASE-T/100BASE-TX INTEGRATED PHYCEIVER™ WITH RMII INTERFACE
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1894KI-40LF
Active10BASE-T/100BASE-TX INTEGRATED PHYCEIVER™ WITH RMII INTERFACE
Deep-Dive with AI
Technical Specifications
Parameters and characteristics commom to parts in this series
Specification | 1894KI-40LF | 1894KI Series |
---|---|---|
Function | - | Physical Layer Controller |
Interface | - | Parallel |
null | - | |
Operating Temperature | - | 85 °C |
Operating Temperature | - | -40 °C |
Package / Case | - | 32-VFQFN Exposed Pad, 32-TFQFN Exposed Pad, 40-TQFN Exposed Pad, 40-VFQFN Exposed Pad |
Protocol | - | Ethernet |
Standards | - | 10/100 Base-T/TX PHY |
Supplier Device Package | - | 32-VFQFPN (5x5), 32-QFN (5x5), 40-QFN (6x6), 40-QFN-EP (6x6) |
Voltage - Supply | - | 3.47 V |
Voltage - Supply | - | 3.14 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Distributor | Package | Quantity | $ | |
---|---|---|---|---|
Digikey | Tray | 490 | $ 5.65 |
1894KI Series
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER™ WITH RMII INTERFACE
Part | Interface | Operating Temperature [Max] | Operating Temperature [Min] | Standards | Supplier Device Package | Package / Case | Voltage - Supply [Max] | Voltage - Supply [Min] | Function | Protocol |
---|---|---|---|---|---|---|---|---|---|---|
Renesas Electronics Corporation 1894KI-32LFT | Parallel | 85 °C | -40 °C | 10/100 Base-T/TX PHY | 32-VFQFPN (5x5) | 32-VFQFN Exposed Pad | 3.47 V | 3.14 V | Physical Layer Controller | Ethernet |
Renesas Electronics Corporation 1894KI-34LF | Parallel | 85 °C | -40 °C | 10/100 Base-T/TX PHY | 32-QFN (5x5) | 32-TFQFN Exposed Pad | 3.47 V | 3.14 V | Physical Layer Controller | Ethernet |
Renesas Electronics Corporation 1894KI-43LF | Parallel | 85 °C | -40 °C | 10/100 Base-T/TX PHY | 40-QFN (6x6) | 40-TQFN Exposed Pad | 3.47 V | 3.14 V | Physical Layer Controller | Ethernet |
Renesas Electronics Corporation 1894KI-33LF | Parallel | 85 °C | -40 °C | 10/100 Base-T/TX PHY | 32-QFN (5x5) | 32-TFQFN Exposed Pad | 3.47 V | 3.14 V | Physical Layer Controller | Ethernet |
Renesas Electronics Corporation 1894KI-40LF | Parallel | 85 °C | -40 °C | 10/100 Base-T/TX PHY | 40-QFN-EP (6x6) | 40-VFQFN Exposed Pad | 3.47 V | 3.14 V | Physical Layer Controller | Ethernet |
Renesas Electronics Corporation 1894KI-33LFT | Parallel | 85 °C | -40 °C | 10/100 Base-T/TX PHY | 32-QFN (5x5) | 32-TFQFN Exposed Pad | 3.47 V | 3.14 V | Physical Layer Controller | Ethernet |
Renesas Electronics Corporation 1894KI-32LFT | ||||||||||
Renesas Electronics Corporation 1894KI-40LF | ||||||||||
Renesas Electronics Corporation 1894KI-34LFT | Parallel | 85 °C | -40 °C | 10/100 Base-T/TX PHY | 32-QFN (5x5) | 32-TFQFN Exposed Pad | 3.47 V | 3.14 V | Physical Layer Controller | Ethernet |
Description
General part information
1894KI Series
The IDT1894-40 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards, ISO/IEC 8802-3. The IDT1894-40 is intended for MII, Node applications that require the Auto-MDIX feature that automatically corrects crossover errors in plant wiring. The IDT1894-40 incorporates Digital-Signal Processing (DSP) control in its Physical-Medium Dependent (PMD) sub layer. As a result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation in excess of 24 dB at 100MHz. With this IDT-patented technology, the IDT1894-40 can virtually eliminate errors from killer packets. The IDT1894-40 provides a Serial-Management Interface for exchanging command and status information with a Station-Management (STA) entity. The IDT1894-40 Media-Dependent Interface (MDI) can be configured to provide either half- or full-duplex operation at data rates of 10 Mb/s or 100Mb/s. In addition, the IDT1894-40 includes a programmable interrupt output function. This function consists of a digital output pin, an interrupt control register, a set of interrupt status register bits and a corresponding set of interrupt enable bits, and a pre-defined set of events which can be assigned as one of the interrupt sources. The purpose of this function is to notify the host of this PHY device when certain event happens via interrupt (the logic level on interrupt output pin going low or going high) instead of polling by the host. The events that could be used to generate interrupts are: receiver error, Jabber, page received, parallel detect fault, link partner acknowledge, link status change, auto-negotiation complete, remote fault, collision, etc.Applications: NIC cards, PC motherboards, switches, routers, DSL and cable modems, game machines, printers, network connected appliances, and industrial equipment.
Documents
Technical documentation and resources