
LTC2230IUP#PBF
ActiveIC ADC 10BIT PIPELINED 64QFN
Deep-Dive with AI
Search across all available documentation for this part.

LTC2230IUP#PBF
ActiveIC ADC 10BIT PIPELINED 64QFN
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | LTC2230IUP#PBF |
|---|---|
| Architecture | Pipelined |
| Configuration | S/H-ADC |
| Data Interface | LVDS - Parallel, Parallel |
| Input Type | Single Ended, Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 1 |
| Number of Bits [custom] | 10 |
| Number of Inputs | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 64-WFQFN Exposed Pad |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | External, Internal |
| Sampling Rate (Per Second) | 170 M |
| Supplier Device Package | 64-QFN (9x9) |
| Voltage - Supply, Analog [Max] | 3.5 V |
| Voltage - Supply, Analog [Min] | 3.1 V |
| Voltage - Supply, Digital [Max] | 3.5 V |
| Voltage - Supply, Digital [Min] | 3.1 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 40 | $ 61.77 | |
Description
General part information
LTC2230 Series
The LTC2230 and LTC2231 are 170Msps/135Msps, sampling 10-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2230/LTC2231 are perfect for demanding communications applications with AC performance that includes 61dB SNR and 75dB spurious free dynamic range for signals up to 200MHz. Ultralow jitter of 0.15psRMSallows undersampling of IF frequencies with excellent noise performance.DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.12LSBRMS.The digital outputs can be either differential LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V.The ENC+and ENC–inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.ApplicationsWireless and Wired Broadband CommunicationCable Head-End SystemsPower Amplifier LinearizationCommunications Test Equipment
Documents
Technical documentation and resources