ZL30102QDG1
ActivePLL CLOCK SYNTHESIZER SINGLE 64-PIN TQFP TRAY
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ZL30102QDG1
ActivePLL CLOCK SYNTHESIZER SINGLE 64-PIN TQFP TRAY
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Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | ZL30102QDG1 | ZL30102 Series |
|---|---|---|
| - | - | |
| Differential - Input:Output | False | False |
| Frequency - Max [Max] | 65.536 MHz | 65.536 MHz |
| Input | Crystal, Clock | Crystal, Clock |
| Main Purpose | T1/E1 | T1/E1 |
| Mounting Type | Surface Mount | Surface Mount |
| Number of Circuits | 1 | 1 |
| Operating Temperature [Max] | 85 °C | 85 °C |
| Operating Temperature [Min] | -40 °C | -40 °C |
| Output | Clock | Clock |
| Package / Case | 64-TQFP | 64-TQFP |
| PLL | True | True |
| Ratio - Input:Output | 3:10 | 3:10 |
| Supplier Device Package | 64-TQFP (10x10) | 64-TQFP (10x10) |
| Voltage - Supply [Max] | 3.63 V | 3.63 V |
| Voltage - Supply [Min] | 2.97 V | 2.97 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 160 | $ 55.19 | |
| Microchip Direct | TRAY | 1 | $ 68.55 | |
| 25 | $ 57.10 | |||
| 100 | $ 51.93 | |||
| 1000 | $ 48.00 | |||
| 5000 | $ 45.51 | |||
ZL30102 Series
PDH System Synchronizer
| Part | Supplier Device Package | Frequency - Max [Max] | Input | Output | Number of Circuits | Main Purpose | Operating Temperature [Max] | Operating Temperature [Min] | Ratio - Input:Output | Package / Case | Voltage - Supply [Min] | Voltage - Supply [Max] | PLL | Mounting Type | Differential - Input:Output |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Microchip Technology ZL30102QDG1 | |||||||||||||||
Microchip Technology ZL30102QDG1 | 64-TQFP (10x10) | 65.536 MHz | Clock, Crystal | Clock | 1 | T1/E1 | 85 °C | -40 °C | 3:10 | 64-TQFP | 2.97 V | 3.63 V | Surface Mount |
Description
General part information
ZL30102 Series
The ZL30102 is a high-performance DPLL (digital phase-locked loop) designed for synchronization and timing control of redundant system clocks requiring Stratum 4/4E timing specifications. The ZL30102 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining a tight phase alignment between redundant primary and secondary system clocks even in the presence of high network jitter.
The ZL30102 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.
Documents
Technical documentation and resources