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LTC2195IUKG#PBF - ANALOG DEVICES LTC2325IUKG-16#PBF

LTC2195IUKG#PBF

Active
Analog Devices

ANALOG TO DIGITAL CONVERTER, 16 BIT, 125 MSPS, DIFFERENTIAL, SINGLE ENDED, SERIAL, SPI, SINGLE

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LTC2195IUKG#PBF - ANALOG DEVICES LTC2325IUKG-16#PBF

LTC2195IUKG#PBF

Active
Analog Devices

ANALOG TO DIGITAL CONVERTER, 16 BIT, 125 MSPS, DIFFERENTIAL, SINGLE ENDED, SERIAL, SPI, SINGLE

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationLTC2195IUKG#PBF
ArchitecturePipelined
ConfigurationS/H-ADC
Data InterfaceLVDS - Serial
FeaturesSimultaneous Sampling
Input TypeDifferential
Mounting TypeSurface Mount
Number of A/D Converters2
Number of Bits16
Number of Inputs2
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case52-WFQFN Exposed Pad
Ratio - S/H:ADC1:1
Reference TypeExternal, Internal
Sampling Rate (Per Second)125 M
Supplier Device Package52-QFN (7x8)
Voltage - Supply, Analog [Max]1.9 V
Voltage - Supply, Analog [Min]1.7 V
Voltage - Supply, Digital [Max]1.9 V
Voltage - Supply, Digital [Min]1.7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 200.82
10$ 196.55
NewarkEach 1$ 200.82
5$ 198.69
10$ 196.55

Description

General part information

LTC2195 Series

The LTC2195/LTC2194/LTC2193 are 2-channel, simultaneous sampling 16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 76.8dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.07psRMSallows undersampling of IF frequencies with excellent noise performance.DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is 3.4LSBRMS.To minimize the number of data lines the digital outputs are serial LVDS. Each channel outputs two bits or four bits at a time. At lower sampling rates there is a one bit per channel option. The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity.The ENC+and ENC–inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.ApplicationsCommunicationsCellular Base StationsSoftware-Defined RadiosPortable Medical ImagingMulti-Channel Data AcquisitionNondestructive Testing