
71V3556SA150BGG
Obsolete3.3V 128KX36 ZBT SYNCHRONOUS PIPELINED SRAM WITH 3.3V I/O

71V3556SA150BGG
Obsolete3.3V 128KX36 ZBT SYNCHRONOUS PIPELINED SRAM WITH 3.3V I/O
Description
General part information
71V3556 Series
The 71V3556 3.3V CMOS synchronous SRAM, organized as 128K x 36, is designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads. Thus, it has been given the name ZBT™, or Zero Bus Turnaround. The 71V3556 contains data I/O, address, and control signal registers.
Technical Specifications
Parameters and characteristics for this part
| Specification | 71V3556SA150BGG |
|---|---|
| Access Time | 3.8 ns |
| Clock Frequency | 150 MHz |
| Memory Depth | 128 K |
| Memory Format | SRAM |
| Memory Interface (Type) | Parallel |
| Memory Size | 4.5 Mbit |
| Memory Type | Volatile |
| Memory Width | 36 bit |
| Mounting Type | Surface Mount |
| Operating Temperature (Max) | 70 °C |
| Operating Temperature (Min) | 0 °C |
| Package / Case | 119-BGA |
| Package Length | 14 mm |
| Package Name | 119-PBGA |
| Package Width | 22 mm |
| Technology | SDR (ZBT), SRAM - Synchronous |
| Voltage - Supply (Maximum) | 3.465 V |
| Voltage - Supply (Minimum) | 3.135 V |
Pricing
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