S25FL512SAGMFI010 is a 512Mb (64MB) FL-S flash non-volatile memory using MirrorBit™ technology that stores two data bits in each memory array transistor, eclipse architecture - that dramatically improves program and erase performance, 65nm process lithography. This device connects to a host system via an SPI. Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for double data rate (DDR) read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock. The Eclipse architecture features a page programming buffer that allows up to 256 words (512bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.