
SY100EL91LZG
ActiveTRANSLATOR LVPECL TO ECL/LVECL 3-CH UNIDIRECTIONAL 20-PIN SOIC W TUBE
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SY100EL91LZG
ActiveTRANSLATOR LVPECL TO ECL/LVECL 3-CH UNIDIRECTIONAL 20-PIN SOIC W TUBE
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Technical Specifications
Parameters and characteristics commom to parts in this series
Specification | SY100EL91LZG | 100EL91 Series |
---|---|---|
- | - | |
Channel Type | Unidirectional | Unidirectional |
Channels per Circuit | 3 | 3 |
Input Signal | LVPECL | PECL, LVPECL |
Mounting Type | Surface Mount | Surface Mount |
Number of Circuits | 1 | 1 |
Operating Temperature [Max] | 85 °C | 85 °C |
Operating Temperature [Min] | -40 °C | -40 - 0 °C |
Output Signal | LVECL, ECL | ECL, LVECL |
Output Type | Differential | Differential |
Package / Case | 20-SOIC | 20-SOIC |
Package / Case [y] | 0.295 in | 0.295 in |
Package / Case [y] | 7.5 mm | 7.5 mm |
Supplier Device Package | 20-SOIC | 20-SOIC |
Translator Type | Mixed Signal | Mixed Signal |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Distributor | Package | Quantity | $ | |
---|---|---|---|---|
Microchip Direct | TUBE | 1 | $ 6.12 | |
25 | $ 5.10 | |||
100 | $ 4.64 | |||
1000 | $ 4.48 | |||
5000 | $ 4.43 | |||
10000 | $ 4.38 |
100EL91 Series
IC TRANSLATOR UNIDIR 20SOIC
Part | Channels per Circuit | Output Type | Operating Temperature [Max] | Operating Temperature [Min] | Package / Case | Package / Case [y] | Package / Case [y] | Translator Type | Input Signal | Channel Type | Supplier Device Package | Number of Circuits | Output Signal | Mounting Type |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Microchip Technology SY100EL91ZG-TR | 3 | Differential | 85 °C | -40 °C | 20-SOIC | 0.295 in | 7.5 mm | Mixed Signal | PECL | Unidirectional | 20-SOIC | 1 | ECL | Surface Mount |
Microchip Technology SY100EL91LZC-TR | 3 | Differential | 85 C | 0 °C | 20-SOIC | 0.295 in | 7.5 mm | Mixed Signal | LVPECL | Unidirectional | 20-SOIC | 1 | ECL, LVECL | Surface Mount |
Microchip Technology SY100EL91ZG | 3 | Differential | 85 °C | -40 °C | 20-SOIC | 0.295 in | 7.5 mm | Mixed Signal | PECL | Unidirectional | 20-SOIC | 1 | ECL | Surface Mount |
Microchip Technology SY100EL91ZC-TR | 3 | Differential | 85 C | 0 °C | 20-SOIC | 0.295 in | 7.5 mm | Mixed Signal | PECL | Unidirectional | 20-SOIC | 1 | ECL | Surface Mount |
Microchip Technology SY100EL91LZI | 3 | Differential | 85 °C | -40 °C | 20-SOIC | 0.295 in | 7.5 mm | Mixed Signal | LVPECL | Unidirectional | 20-SOIC | 1 | ECL, LVECL | Surface Mount |
Microchip Technology SY100EL91ZC | 3 | Differential | 85 C | 0 °C | 20-SOIC | 0.295 in | 7.5 mm | Mixed Signal | PECL | Unidirectional | 20-SOIC | 1 | ECL | Surface Mount |
Microchip Technology SY100EL91LZG | 3 | Differential | 85 °C | -40 °C | 20-SOIC | 0.295 in | 7.5 mm | Mixed Signal | LVPECL | Unidirectional | 20-SOIC | 1 | ECL, LVECL | Surface Mount |
Microchip Technology SY100EL91LZC | 3 | Differential | 85 C | 0 °C | 20-SOIC | 0.295 in | 7.5 mm | Mixed Signal | LVPECL | Unidirectional | 20-SOIC | 1 | ECL, LVECL | Surface Mount |
Microchip Technology SY100EL91LZG |
Description
General part information
100EL91 Series
The SY100EL91L is a triple LVPECL-to-ECL or LVPECL-to-LVECL translator. A VBB output is provided for interfacing with single ended PECL signals at the input. If a single ended input is to be used, the VBB output should be connected to the D input. The active signal would then drive the D input. When used, the VBB output should be bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the EL91L under single ended input switching conditions. As a result this pin can only source/sink up to 0.5mA of current.To accomplish the level translation the EL91L requires three power rails. The VCC supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GND pins as expected are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01µF capacitors.Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled to GND. This condition will force the Q output to a LOW, ensuring stability.
Documents
Technical documentation and resources