S28HS512TGABHI010 is a SEMPER™ flash memory. It is a high-speed CMOS, MIRRORBIT™ NOR flash device that is compliant with the JEDEC JESD251 eXpanded SPI (xSPI) specification. SEMPER™ is designed for functional safety with development according to ISO 26262 standard to achieve ASIL-B compliance and ASIL-D readiness. SEMPER™ Flash provides a flexible sector architecture. The device control logic is subdivided into two parallel operating sections: the host interface controller (HIC) and the embedded algorithm controller (EAC). The HIC monitors signal levels on the device inputs and drives outputs as needed to complete read, program, and write data transfers with the host system. The SEMPER™ flash with octal interface device supports error detection and correction by generating an embedded hamming error correction code during memory array programming.