
NCP51145PDR2G
ObsoleteSOURCE AND SINK BUS TERMINATION REGULATOR 1V TO 5.5V 8-PIN SOIC N EP T/R

NCP51145PDR2G
ObsoleteSOURCE AND SINK BUS TERMINATION REGULATOR 1V TO 5.5V 8-PIN SOIC N EP T/R
Description
General part information
NCP51145PDR2G
The NCP51145 is a linear regulator designed to supply a regulated VTT termination voltage for DDR−II, DDR−III, LPDDR−III and DDR−IV memory applications. The regulator is capable of actively sourcing and sinking ±1.8 A peak currents while regulating an output voltage to within ±20 mV. The output termination voltage is regulated to track VDDQ / 2 by two external voltage divider resistors connectedto the PVCC, GND, and VREF pins.The NCP51145 incorporates a high−speed differential amplifier to provide ultra−fast response to line and load transients. Other features include source/sink current limiting, soft−start and on−chip thermal shutdown protection.
Technical Specifications
Parameters and characteristics for this part
| Specification | NCP51145PDR2G |
|---|---|
| Applications | LDO (Linear), DDR |
| Mounting Type | Surface Mount |
| Number of Outputs | 1 |
| Operating Temperature (Max) | 85 °C |
| Operating Temperature (Min) | -40 °C |
| Package Features | Exposed Pad |
| Package Length | 0.154 in |
| Package Name | 8-SOIC, 8-SOIC-EP |
| Package Width | 3.9 mm |
| Voltage - Input (Maximum) | 5.5 V |
| Voltage - Input (Minimum) | 1 V |
Pricing
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