CY7C1061GE30-10ZSXI is a high-performance CMOS fast static RAM device with embedded ECC. It is offered in single and dual chip enable options and in multiple pin configurations. The CY7C1061GE device includes an ERR pin that signals a single-bit error-detection and correction event during a read cycle. To access devices with a single chip enable input, assert the chip enable (active low CE) input LOW. To access dual chip enable devices, assert both chip enable inputs – active low CE1 as LOW and CE2 as HIGH. To perform data writes, assert the write enable (active low WE) input LOW, and provide the data and address on the device data pins (I/O0 through I/O15) and address pins (A0 through A19) respectively. The byte high enable (active low BHE) and byte low enable (active low BLE) inputs control byte writes, and write data on the corresponding I/O lines to the memory location specified. Active low BHE controls I/O8 through I/O15 and active low BLE controls I/O0 through I/O7.