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SY88933ALKG-TR - MSOP / 10

SY88933ALKG-TR

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Microchip Technology

SP AMP LIMITING POST AMPLIFIER SINGLE 3.6V 10-PIN MSOP T/R

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SY88933ALKG-TR - MSOP / 10

SY88933ALKG-TR

Active
Microchip Technology

SP AMP LIMITING POST AMPLIFIER SINGLE 3.6V 10-PIN MSOP T/R

Technical Specifications

Parameters and characteristics commom to parts in this series

SpecificationSY88933ALKG-TRSY88933AL Series
ApplicationsOptical NetworksOptical Networks
Mounting TypeSurface MountSurface Mount
Package / Case10-MSOP, 10-TFSOP10-MSOP, 10-TFSOP
Package / Case [x]3 mm3 mm
Package / Case [x]0.118 in0.118 in
Supplier Device Package10-MSOP10-MSOP

SY88933AL Series

IC LIMIT AMP 10MSOP

PartApplicationsPackage / CasePackage / Case [x]Package / Case [x]Mounting TypeSupplier Device Package
Microchip Technology
SY88933ALKG
Optical Networks
10-MSOP, 10-TFSOP
3 mm
0.118 in
Surface Mount
10-MSOP
Microchip Technology
SY88933ALKG-TR
Optical Networks
10-MSOP, 10-TFSOP
3 mm
0.118 in
Surface Mount
10-MSOP

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
Microchip DirectT/R 1$ 8.44
25$ 7.02
100$ 6.39
1000$ 5.32
5000$ 4.92
10000$ 4.57

Description

General part information

SY88933AL Series

The SY88933AL high-sensitivity limiting post amplifier is designed for use in fiber-optic receivers. The device connects to typical transimpedance amplifiers (TIAs). The linear signal output from TIAs can contain significant amounts of noise and may vary in amplitude over time. The SY88933AL quantizes these signals and outputs PECL level waveforms.

The SY88933AL operates from a single +3.3V power supply, over temperatures ranging from -40°C to +8°C. With its wide bandwidth and high gain, signal with data rates up to 1.25Gbps and as small as 5mVPP can be amplified to drive devices with PECL inputs.

The SY88933AL generates a high gain signal-detect (SD) open-collector TTL output. The SD function has a high gain input stage for increased sensitivity. A programmable signal-detect level set pin (SDLVL) sets the sensitivity of the input amplitude detection. SD asserts high if the input amplitude rises above the threshold set by SDLVL and de-asserts low otherwise. The enable input (EN) de-asserts the true output signal without removing the input signal. The SD output can be fed back to the EN input to maintain output stability under a loss-of-signal condition. Typically, 3.4dB SD hysteresis is provided to prevent chattering.