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2059GI-02LF - 2059-02 - Block Diagram

2059GI-02LF

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Renesas Electronics Corporation

CLOCK MULTIPLIER AND JITTER ATTENUATOR

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2059GI-02LF - 2059-02 - Block Diagram

2059GI-02LF

Active
Renesas Electronics Corporation

CLOCK MULTIPLIER AND JITTER ATTENUATOR

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Technical Specifications

Parameters and characteristics commom to parts in this series

Specification2059GI-02LF2059-02 Series
Differential - Input:Output-False
Frequency - Max-27 MHz
Input-Crystal, Clock
Mounting Type-Surface Mount
null-
Number of Circuits-1
Operating Temperature-85 °C
Operating Temperature--40 °C
Output-CMOS
Package / Case-0.173 in
Package / Case-16-TSSOP
Package / Case-4.4 mm
PLL-True
Ratio - Input:Output-2:1
Supplier Device Package-16-TSSOP
Type-Jitter Attenuator, Multiplexer
Voltage - Supply-3.45 V
Voltage - Supply-3.15 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$

2059-02 Series

Clock Multiplier And Jitter Attenuator

PartRatio - Input:OutputMounting TypePackage / Case [x]Package / CasePackage / Case [y]OutputTypeInputPLLVoltage - Supply [Max]Voltage - Supply [Min]Supplier Device PackageFrequency - Max [Max]Differential - Input:OutputNumber of CircuitsOperating Temperature [Max]Operating Temperature [Min]
Renesas Electronics Corporation
2059GI-02LF
Renesas Electronics Corporation
2059GI-02LFT
2:1
Surface Mount
0.173 in
16-TSSOP
4.4 mm
CMOS
Jitter Attenuator, Multiplexer
Clock, Crystal
3.45 V
3.15 V
16-TSSOP
27 MHz
1
85 °C
-40 °C
Renesas Electronics Corporation
2059GI-02LFT

Description

General part information

2059-02 Series

The 2059-02 is a VCXO (Voltage Controlled Crystal Oscillator) based clock multiplier and jitter attenuator designed for system clock distribution applications. This monolithic IC, combined with an external inexpensive quartz crystal, can be used to replace a more costly hybrid VCXO retiming module. A dual input mux is also provided. By controlling the VCXO frequency within a phase-locked loop (PLL), the output clock is phase and frequency locked to the input clock. Through selection of external loop filter components, the PLL loop bandwidth and damping factor can be tailored to meet system clock requirements. A loop bandwidth down to the Hz range is possible.

Documents

Technical documentation and resources