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SY100EL17VZC - 20 SOIC

SY100EL17VZC

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Microchip Technology

IC RCVR QUAD DIFF 5V/3.3V 20SOIC

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SY100EL17VZC - 20 SOIC

SY100EL17VZC

Active
Microchip Technology

IC RCVR QUAD DIFF 5V/3.3V 20SOIC

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics commom to parts in this series

SpecificationSY100EL17VZC100EL17 Series
Logic TypeDifferential ReceiverDifferential Receiver
Mounting TypeSurface MountSurface Mount
Number of Bits44
Operating Temperature [Max]85 °C85 °C
Operating Temperature [Min]-40 °C-40 °C
Package / Case20-SOIC20-SOIC
Package / Case [y]0.295 in0.295 in
Package / Case [y]7.5 mm7.5 mm
Supplier Device Package20-SOIC20-SOIC
Supply Voltage5 V, 3.3 V3.3 - 5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$

100EL17 Series

Quad Differential Receiver

PartOperating Temperature [Max]Operating Temperature [Min]Package / CasePackage / Case [y]Package / Case [y]Supply VoltageLogic TypeNumber of BitsSupplier Device PackageMounting Type
Microchip Technology
SY100EL17VZG
85 °C
-40 °C
20-SOIC
0.295 in
7.5 mm
3.3 V, 5 V
Differential Receiver
4
20-SOIC
Surface Mount
Microchip Technology
SY100EL17VZI-TR
85 °C
-40 °C
20-SOIC
0.295 in
7.5 mm
3.3 V, 5 V
Differential Receiver
4
20-SOIC
Surface Mount
Microchip Technology
SY100EL17VZC
85 °C
-40 °C
20-SOIC
0.295 in
7.5 mm
3.3 V, 5 V
Differential Receiver
4
20-SOIC
Surface Mount

Description

General part information

100EL17 Series

The SY100EL17V is a quad differential receiver. The device is functionally equivalent to the E116 device with the capability of operation from either a ECL supply voltage (-3.3V or -5V) or PECL supply voltage (+3.3V or +5V).The EL17V provides a VBB output for either single-ended use or as a DC bias for AC coupling to the device. The VBBpin should be used only as a bias for the EL17V as its current sink/source capability is limited.Whenever used, the VBB pin should be bypassed to ground via a 0.01µf capacitor.Under open input conditions, the /D input will be biased at VCC/2 and the D input will be pulled down to VEE. This operation will force the Q output LOW and ensure stability.

Documents

Technical documentation and resources