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527R-01ILF - 28-SSOP

527R-01ILF

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Renesas Electronics Corporation

IC FANOUT BUFFER 28QSOP

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527R-01ILF - 28-SSOP

527R-01ILF

Active
Renesas Electronics Corporation

IC FANOUT BUFFER 28QSOP

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics commom to parts in this series

Specification527R-01ILF527R Series
Differential - Input:OutputFalseFalse
Differential - Input:Output-Yes/No
Frequency - Max [Max]140 MHz140 - 160 MHz
InputClockClock, PECL
Mounting TypeSurface MountSurface Mount
Number of Circuits11
Operating Temperature [Max]85 °C70 - 85 °C
Operating Temperature [Min]-40 °C-40 - 0 °C
OutputClockClock, CMOS
Package / Case28-SSOP28-SSOP
PLLTrueTrue
Ratio - Input:Output [custom]1:21:2
TypeZero Delay Buffer, Fanout Buffer (Distribution)Zero Delay Buffer, Fanout Buffer (Distribution)
Voltage - Supply [Max]3.6 V3.465 - 3.6 V
Voltage - Supply [Min]3 V3 - 3.135 V

527R Series

Clock Slicer User Configurable Zero Delay Buffer

PartFrequency - Max [Max]Package / CaseNumber of CircuitsOutputVoltage - Supply [Max]Voltage - Supply [Min]TypeMounting TypePLLDifferential - Input:OutputRatio - Input:Output [custom]InputOperating Temperature [Max]Operating Temperature [Min]Differential - Input:Output
Renesas Electronics Corporation
527R-01LFT
160 MHz
28-SSOP
1
Clock
3.6 V
3 V
Fanout Buffer (Distribution), Zero Delay Buffer
Surface Mount
1:2
Clock
70 °C
0 °C
Renesas Electronics Corporation
527R-01ILF
140 MHz
28-SSOP
1
Clock
3.6 V
3 V
Fanout Buffer (Distribution), Zero Delay Buffer
Surface Mount
1:2
Clock
85 °C
-40 °C
Renesas Electronics Corporation
527R-02LF
160 MHz
28-SSOP
1
CMOS
3.465 V
3.135 V
Fanout Buffer (Distribution), Zero Delay Buffer
Surface Mount
1:2
PECL
70 °C
0 °C
Yes/No

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 200$ 2.90

Description

General part information

527R Series

The 527-01 Clock Slicer is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. A SYNC pulse indicates when the rising clock edges are aligned with zero skew. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The 527-01 aligns rising edges on ICLK and FBIN at a ratio determined by the reference and feedback dividers. For configurable clocks that do not require zero delay, use the 525.

Documents

Technical documentation and resources